As semiconductor technology continues to inch closer to practical limitations in terms of feature size, architects are increasingly focusing on alternative manners of meeting the demands for integrating increasingly complex circuitry onto semiconductor devices, or chips. In addition, as feature sizes decrease, and thus as faster and more complex circuits are integrated onto a given semiconductor chip, architects are finding that in many instances the communication of data between the various functional units on a semiconductor chip can become a bottleneck on overall performance. Communicating data between functional units disposed at opposite ends of a large semiconductor chip (e.g., a 300 or 500 mm2 die size) often requires several clock cycles, as well as significant buffering logic on the chip. Furthermore, in general as the size and amount of circuitry integrated into a chip design increases, the yield of the manufacturing process typically decreases, thereby increasing the cost of the manufactured chips.
One proposed solution to address these limitations has been to physically and electrically couple together multiple semiconductor chips or dies into a stack arrangement. By doing so, individual chips that are smaller, less complex, and less expensive can be used in lieu of a single larger, more complex and more expensive chip, and often with comparable or better overall performance. In many instances, for example, it has been found that the vertical distance between circuit logic disposed in different layers of a multi-layer semiconductor stack may end up being shorter than the maximum horizontal distances within any given circuit layer, and as such, communicating data between circuit layers disposed on different chips may involve less latency than communicating data between distant points on the same chip. Some conventional stacking technologies, for example, are capable of separating circuit layers on adjacent dies in a stack by less than 100 um, which is an order of magnitude or more less than the maximum horizontal dimension of many dies (e.g., a 100 mm2 die has a length and width of 10,000 um).
From a design standpoint, however, integrating circuits on multiple chips in a multi-layer semiconductor stack can be problematic. Laying out signal paths and electrical conductors to effectively interconnect circuits conventionally has required substantial design work, and opportunities for design reuse have been limited.
Another challenge for multi-layer semiconductor stacks is associated with the tradeoffs required when using different types of fabrication technologies. Traditionally, multi-layer semiconductor stacks have been formed using either chip-chip bonding or wafer-wafer bonding. Chip-chip bonding involves separating the semiconductor chips from their respective wafers prior to bonding the chips together in a stack, while wafer-wafer bonding involves bonding the chips in a stack together while they are still in wafer form, so that the separation from the wafer occurs after bonding has been performed.
Chip-chip bonding has the benefit that the chips are not constrained by size or aspect ratio, so practically any combination of chips, within reasonable limits, can be bonded together. Chip-chip bonding also can be used to bond practically any number of chips together in a stack. Furthermore, chips can be tested prior to bonding, thus enabling defective chips to be sorted out and discarded, thereby providing a higher yield for the overall stack arrangements. A primary drawback of chip-chip bonding, however, is that the interconnect density is typically limited by the need to align chips during the bonding process.
In contrast, wafer-wafer bonding allows for a substantially higher interconnect density than chip-chip bonding, but it suffers from a number of drawbacks. First, all chips in a wafer-wafer bonding process much be of identical size and aspect ratio. Second, wafer-wafer bonding is inherently a two chip stack process, so it cannot be used to bond together three or more chips in a stack. Third, wafer-wafer bonding is subject to the exponential problem with respect to yields, so it is often necessary to limit its use to situations where one of the wafers includes circuit logic that has a near 100% yield (e.g., memory arrays). Otherwise, the yields of the two wafers must effectively be multiplied, resulting in a substantially lower yield than the normal yield of a single semiconductor chip.
Therefore, a significant need exists in the art for an improved process for bonding together chips in a multi-layer semiconductor stack.